A pad router for the Monterey Silicon Compiler

Download
Author
Rexach, Carlos Francisco.
Date
1988Advisor
Kirk, Donald E.
Metadata
Show full item recordAbstract
A two layer pad router is developed for the Monterey Silicon Compiler. Features include an improved pad placement routine that extracts information from the internal layout to minimize chip area and wiring lengths, and a track allocation algorithm that minimizes the use of polysilicon during net layout. The router's performance was compared to that of the MacPitt's Silicon Compiler with four distinct circuits. The Monterey pad router layouts were 5% to 25% faster, and 10% to 15% smaller than those produced by MacPitts. Keywords: VLSI design, MacPitts, Silicon compiler, CAD Tools, Pad router, Pad placement, Router, Theses. (kt)
Collections
Related items
Showing items related by title, author, creator and subject.
-
On Route Aggregation
Le, F.; Zhang, H.; Xie, Geoffrey (2011-12);Route Aggregation (RA), the method to supersede a set of routes by a single, more general route, is a fundamental mechanism to the Internet scalability. Yet, despite its importance, it is poorly understood. We present the ... -
Prototyping of an active and lightweight router
Kaplan, Namik (Monterey, California. Naval Postgraduate School, 1999-03-01);A new network management system named Server and Agent based Active Management (SAAM) has been proposed. SAAM can locate and fix network problems much more quickly than today's systems. Stand-alone routers are used in ... -
The many facets of Internet topology and traffic
Alderson, D.; Chang, H.; Roughan, M; Uhlig, S.; Willinger, W. (American Institute of Mathematical Sciences, 2006-12);The Internet's layered architecture and organizational structure give rise to a number of different topologies, with the lower layers defining more physical and the higher layers more virtual/logical types of connectivity ...