Design of multiple-valued programmable logic arrays
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Authors
Ko, Yong Ha
Subjects
Multiple-valued logic function
Programmable logic array
Circuit generation
Simulation
Programmable logic array
Circuit generation
Simulation
Advisors
Butler, Jon T.
Date of Issue
1988-12
Date
December 1988
Publisher
Language
en_US
Abstract
The goal of this thesis is the development of a programmable logic array (PLA) that accepts multiple-valued inputs and produces multiple valued outputs. The
PLA is implemented in CMOS and multiple levels are encoded as current. It is programmed by choosing transistor geometries which control the current level at
which the PLA reacts to inputs. An example of a 4-valued PLA is shown. As part of this research, a C program was written that produces a PLA layout.
Type
Thesis
Description
Series/Report No
Department
Electrical and Computer Engineering
Organization
Naval Postgraduate School (U.S.)
Identifiers
NPS Report Number
Sponsors
Funder
Format
61 p.
Citation
Distribution Statement
Approved for public release; distribution is unlimited.
Rights
Copyright is reserved by the copyright owner