Design of multiple-valued programmable logic arrays
Ko, Yong Ha
Butler, Jon T.
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The goal of this thesis is the development of a programmable logic array (PLA) that accepts multiple-valued inputs and produces multiple valued outputs. The PLA is implemented in CMOS and multiple levels are encoded as current. It is programmed by choosing transistor geometries which control the current level at which the PLA reacts to inputs. An example of a 4-valued PLA is shown. As part of this research, a C program was written that produces a PLA layout.
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Kerkhoff, Hans G.; Butler, Jon T. (1987-07);As in binary, a multiple-valued programmable logic array (PLA) realises a sum-of-products, expression specified by the user. However, in multiple-valued logic, there are many more operations than in binary, and an important ...
Sasao, T.; Butler, Jon T. (2003-05);We consider the path length in decision diagrams for multiple-valued functions. This is an important measure of a decision diagram, since this models the time needed to evaluate the function. We consider the path length ...
HAMLET - An expression compiler/optimizer for the implementation of heuristics to minimize multiple-valued programmable logic arrays Yurchak, John M.; Butler, Jon T. (1990-05);HAMLET is a CAD tool that translates a user specification of a multiple-valued expression into a layout of a multiple-valued programmable logic array (MVL-PLA) which realizes that expression. It is modular to accommodate ...