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dc.contributor.advisorBerzins, Valdis
dc.contributor.authorSchweiger, Jeffrey Mark
dc.date.accessioned2012-11-29T16:14:13Z
dc.date.available2012-11-29T16:14:13Z
dc.date.issued1992
dc.identifier.urihttp://hdl.handle.net/10945/23630
dc.description.abstractThis thesis describes a conceptual design for a software tool for automatic detection of synchronization constraint deadlock from the formal specification of a distributed system. The formal specification language Spec is used to define the distributed system. The basic algorithm used is introduced using a graphical representation, and its operation illustrated via an example.en_US
dc.description.urihttp://archive.org/details/detectingpotenti1094523630
dc.format.extent70 p.;28 cm.en_US
dc.language.isoen_US
dc.publisherMonterey, California. Naval Postgraduate Schoolen_US
dc.titleDetecting potential synchronization constraint deadlocks from formal system specifications.en_US
dc.typeThesisen_US
dc.contributor.secondreaderLuqi
dc.contributor.corporateNaval Postgraduate School
dc.contributor.schoolNaval Postgraduate School
dc.contributor.departmentComputer Science
dc.description.serviceLieutenant Commander, United States Navyen_US
etd.thesisdegree.nameM.S. in Computer Scienceen_US
etd.thesisdegree.levelMastersen_US
etd.thesisdegree.disciplineComputer Scienceen_US
etd.thesisdegree.grantorNaval Postgraduate Schoolen_US
dc.description.distributionstatementApproved for public release; distribution is unlimited.


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