A digital hardware test system analysis with test vector translation
Loeblein, James T.
Loomis, Harold H., Jr.
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Digital logic testing occurs in two different test environments, digital simulation and actual hardware testing. A computer aided design (CAD) tool applies a set of stimulus/response test vector patterns to check the functionality of a digital circuit design. Once manufactured, the chip with this design is tested by a hardware tester system (i.e. automatic test equipment (ATE)). The ATE performs many tests in addition to the functionality test. However the stimulus/response test vector formats used in these two environments are different and, therefore, incompatible in present form. This thesis is aimed at two major objectives. first, a system study will be performed on the GenRad-125 VLSI Hardware Tester System, including its usage, test capabilities and limitations. Secondly, this thesis addresses the problem of test vector format incompatibility between the two testing environments. Special UNIX tools, Lex and Yacc, are used to create a software translator which changes the CAD simulation file into the GenRad-125 Hardware Test System format.
RightsThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.
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