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dc.contributor.advisorLee, Chin-Hwa
dc.contributor.authorLoeblein, James T.
dc.dateDecember 1992
dc.date.accessioned2012-11-29T16:14:19Z
dc.date.available2012-11-29T16:14:19Z
dc.date.issued1992-12
dc.identifier.urihttp://hdl.handle.net/10945/23643
dc.descriptionApproved for public release; distribution is unlimiteden_US
dc.description.abstractDigital logic testing occurs in two different test environments, digital simulation and actual hardware testing. A computer aided design (CAD) tool applies a set of stimulus/response test vector patterns to check the functionality of a digital circuit design. Once manufactured, the chip with this design is tested by a hardware tester system (i.e. automatic test equipment (ATE)). The ATE performs many tests in addition to the functionality test. However the stimulus/response test vector formats used in these two environments are different and, therefore, incompatible in present form. This thesis is aimed at two major objectives. first, a system study will be performed on the GenRad-125 VLSI Hardware Tester System, including its usage, test capabilities and limitations. Secondly, this thesis addresses the problem of test vector format incompatibility between the two testing environments. Special UNIX tools, Lex and Yacc, are used to create a software translator which changes the CAD simulation file into the GenRad-125 Hardware Test System format.en_US
dc.description.urihttp://archive.org/details/digitalhardwaret00loeb
dc.format.extent94 p.en_US
dc.language.isoen_US
dc.publisherMonterey, California. Naval Postgraduate Schoolen_US
dc.rightsThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.en_US
dc.titleA digital hardware test system analysis with test vector translationen_US
dc.typeThesisen_US
dc.contributor.secondreaderLoomis, Harold H., Jr.
dc.contributor.corporateNaval Postgraduate School
dc.contributor.departmentDepartment of Electrical and Computer Engineering
dc.subject.authorDigital testingen_US
dc.subject.authorSimulationen_US
dc.subject.authorLexen_US
dc.subject.authorYaccen_US
dc.subject.authorLanguage translationen_US
dc.subject.authorTest vectoren_US
dc.description.serviceLieutenant, United States Navyen_US
etd.thesisdegree.nameM.S. in Electrical Engineeringen_US
etd.thesisdegree.levelMastersen_US
etd.thesisdegree.disciplineElectrical Engineeringen_US
etd.thesisdegree.grantorNaval Postgraduate Schoolen_US


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