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dc.contributor.advisorFouts, Douglas J.
dc.contributor.authorVagts, Christopher Bryan
dc.date.accessioned2012-11-29T16:19:16Z
dc.date.available2012-11-29T16:19:16Z
dc.date.issued1992-12
dc.identifier.urihttp://hdl.handle.net/10945/24038
dc.descriptionApproved for public release; distribution is unlimiteden_US
dc.description.abstractThis thesis presents the design and layout of a Gallium Arsenide (GaAs) Dynamic Random Access Memory (DRAM) cell. Attempts have been made at producing GaAs DRAM cells, but these have dealt with modifications to the fabrication process, are expensive, and have met with little success. An eight-address by one-bit memory is designed, simulated, and laid out for a standard GaAs digital fabrication process. Three different configurations of RAM cells are considered: the Three-Transistor RAM Cell, the One-Transistor RAM Cell with a Diode and the One-Transistor RAM Cell with a capacitor. All are tested and compared using the circuit simulator HSPICE. The chosen DRAM design uses the One- Transistor RAM Cell with a parallel plate capacitor and a five-transistor differential sense amplifier that handles reading as well as refresh of the memory cells. The differential sense amplifier compares a dummy cell with a memory cell to perform a read. The required timing is presented and demonstrated with read, write, and refresh cycles. Actions to minimize charge leakage are also considered and discussed. The design is simulated for access rates of approximately five nanoseconds, but the basic design can work at much faster rates with little modification.en_US
dc.description.urihttp://archive.org/details/singletransistor00vagt
dc.format.extent88 p.;28 cm.en_US
dc.language.isoen_US
dc.publisherMonterey, California. Naval Postgraduate Schoolen_US
dc.titleA single-transistor memory cell and sense amplifier for a gallium arsenide dynamic random access memoryen_US
dc.typeThesisen_US
dc.contributor.secondreaderLoomis, Herschel H.
dc.contributor.corporateNaval Postgraduate School
dc.contributor.schoolNaval Postgraduate School
dc.contributor.departmentElectrical Engineering
dc.subject.authorRAMen_US
dc.subject.authorDRAMen_US
dc.subject.authorGallium Arsenide DRAMen_US
dc.subject.authorCharge Storage in DRAM Cellsen_US
dc.description.serviceLieutenant Commander, United States Navyen_US
etd.thesisdegree.nameM.S. in Electrical Engineeringen_US
etd.thesisdegree.levelMastersen_US
etd.thesisdegree.disciplineElectrical Engineeringen_US
etd.thesisdegree.grantorNaval Postgraduate Schoolen_US


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