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dc.contributor.advisorZaky, Amr
dc.contributor.authorTharpe, Leonard.
dc.dateSeptember 1992
dc.date.accessioned2012-11-29T16:19:23Z
dc.date.available2012-11-29T16:19:23Z
dc.date.issued1992-09
dc.identifier.urihttp://hdl.handle.net/10945/24057
dc.descriptionApproved for public release; distribution is unlimiteden_US
dc.description.abstractThis thesis presents a simulation and analysis of the Reduced Instruction Set Computer (RISC) architecture and the effects on RISC performance of a lockup-free cache interface. RISC architectures achieve high performance by having a small, but sufficient, instruction set with most instructions executing in one clock cycle. Current RISC performance range from 1.5 to 2.0 CPI. The goal of RISC is to attain a CPI of 1.0. The major hindrance in attaining that goal is attributed to instructions that require main memory access. In this thesis, we attempt to reduce the effects of the high penalties for non-cache accesses by using a non-blocking cache memory subsystem called a lockup-free cache. This interface between the cache and main memory prevents the processor from "locking up" when a request from main memory occurs. This is accomplished by entering all non-cache requests into a memory request queue, while the processor continues to issue and execute other instructions. The evaluation of the effects of the lockup-free cache interface is done using different variation of the interface design. The results show that using the lockup-free cache improves the RISC performance.en_US
dc.description.urihttp://archive.org/details/studyoneffective00thar
dc.format.extent127 p.en_US
dc.language.isoen_US
dc.publisherMonterey, California. Naval Postgraduate Schoolen_US
dc.rightsThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.en_US
dc.titleA study on the effectiveness of lockup-free caches for a Reduced Instruction Set Computer (RISC) processoren_US
dc.typeThesisen_US
dc.contributor.secondreaderNelson, Michael L.
dc.contributor.corporateNaval Postgraduate School (U.S.)
dc.contributor.departmentDepartment of Computer Science
dc.subject.authorReduced Instruction Set Computer (RISC)en_US
dc.subject.authorLockup-free cache interfaceen_US
dc.description.serviceCaptain, United States Armyen_US
etd.thesisdegree.nameMaster of Computer Scienceen_US
etd.thesisdegree.levelMastersen_US
etd.thesisdegree.disciplineComputer Scienceen_US
etd.thesisdegree.grantorNaval Postgraduate Schoolen_US


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