Publication:
Implementation of a fault tolerant control unit within an FPGA for space applications

Loading...
Thumbnail Image
Authors
Perez Casanova, Gaspar M.
Subjects
Advisors
Loomis, Herschel H.
Ross, Alan A.
Date of Issue
2006-12
Date
Publisher
Monterey, CA; Naval Postgraduate School
Language
Abstract
The space environment implies a challenge for the development and utilization of electronics. Field Programmable Gate Arrays (FPGAs) represent a possible solution to that challenge. An FPGA itself is not a Fault Tolerant component, but with the correct configuration it can emulate and behave as one. The Configurable Fault Tolerant Processor (CFTP) developed at the Naval Postgraduate School (NPS) was intended to work as a platform for the implementation and testing of designs and experiments for space applications. The mayor components of the CFTP are two FPGAs, one configured as the control FPGA (X1) and the other as the experiment FPGA (X2). The configuration of the experiment FPGA already includes fault tolerant properties against radiation and its effects over FPGAs. The control experiment did not have any fault tolerance built-in. This thesis investigates the design, considerations, implementation, performance and resource utilization of a Fault Tolerant Control Unit based on FPGA technology using a Triple Modular Redundancy (TMR) approach.
Type
Thesis
Description
Series/Report No
Organization
Naval Postgraduate School (U.S.)
Identifiers
NPS Report Number
Sponsors
Funder
Format
xx, 83 p. : col. ill. ;
Citation
Distribution Statement
Approved for public release; distribution is unlimited.
Rights
Collections