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dc.contributor.advisorLoomis, Herschel H., Jr.
dc.contributor.authorCorliss, Walter F., II
dc.dateMarch 1989
dc.date.accessioned2013-01-23T22:08:48Z
dc.date.available2013-01-23T22:08:48Z
dc.date.issued1989-03
dc.identifier.urihttp://hdl.handle.net/10945/27024
dc.descriptionApproved for public release; distribution is unlimiteden_US
dc.description.abstractThe engineering methodology for producing a fully tested VLSI chip from a design layout is presented. A 16-bit correlator, NPS CORN88, that was previously designed, was used as a vehicle to demonstrate this methodology. The study of the design and simulation tools, MAGIC and MOSSIM II, was the focus of the design and validation process. The design was then implemented and the chip was fabricated by MOSIS. This fabricated chip was then used to develop a testing methodology for using the digital test facilities at NPS. NPS CORN88 was the first full custom VLSI chip, designed at NPS, to be tested with the NPS digital analysis system, Tektronix DAS 9100 series tester. The capabilities and limitations of these test facilities are examined within this thesis. NPS CORN88 test results are included to demonstrate the capabilities of the digital test system. A translator, MOS2DAS, was developed to convert the MOSSIM II simulation program to the input files required by the DAS 9100 device verification software, 91DVS. Finally, a tutorial for using the digital test facilities, including the DAS 9100 and associated support equipments, is included as an appendix.en_US
dc.description.urihttp://archive.org/details/engineeringmetho00corl
dc.format.extent110 p.en_US
dc.language.isoen_US
dc.publisherMonterey, California. Naval Postgraduate Schoolen_US
dc.rightsThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.en_US
dc.titleAn engineering methodology for implementing and testing VLSI circuitsen_US
dc.typeThesisen_US
dc.contributor.secondreaderYang, Chyan
dc.contributor.corporateNaval Postgraduate School (U.S.)
dc.contributor.departmentDepartment of Electrical and Computer Engineering
dc.subject.authorVLSIen_US
dc.subject.authorMAGICen_US
dc.subject.authorMOSSIM IIen_US
dc.subject.authorDVS50en_US
dc.subject.authorDigital test facilitiesen_US
dc.description.serviceLieutenant Commander, United States Navyen_US
etd.thesisdegree.nameM.S. in Electrical Engineeringen_US
etd.thesisdegree.levelMastersen_US
etd.thesisdegree.disciplineElectrical Engineeringen_US
etd.thesisdegree.grantorNaval Postgraduate Schoolen_US


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