Publication:
Implementation of a design for testability strategy using the Genesil silicon compiler

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Authors
Davidson, John Carl
Subjects
Design for testability
Scanpath
Built-in test
Genesil shiftable test latch
Silicon compiler
Linear feedback shift register
Advisors
Loomis, Herschel H., Jr.
Date of Issue
1989-03
Date
March 1989
Publisher
Monterey, California. Naval Postgraduate School
Language
en_US
Abstract
Design for Testability (DFT) is receiving major emphasis in the very large scale integration design field due to increasing circuit complexity. The utility of the silicon compiler and its value to a system designer without extensive VLSI design experience is discussed. Two major techniques for DFT, Scanpath Design and Built-in Test Design, are implemented using the Genesil silicon compiler. The basic building block, the shiftable test latch, is described in random logic block form and parallel datapath form. Linear feedback shift registers used as random vector generators and signature analyzers are used in the Built-in Test design. An Automatic Test Generation program is used to provide a measure of fault coverage for the two DFT techniques. The appendix is a brief tutorial illustrating the use of the Genesil system's shiftable test latch in its different configurations
Type
Thesis
Description
Series/Report No
Department
Department of Electrical and Computer Engineering
Organization
Naval Postgraduate School (U.S.)
Identifiers
NPS Report Number
Sponsors
Funder
Format
115 p.
Citation
Distribution Statement
Approved for public release; distribution is unlimited.
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.
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