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Implementation of a design for testability strategy using the Genesil silicon compiler

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Author
Davidson, John Carl
Date
1989-03
Advisor
Loomis, Herschel H., Jr.
Second Reader
Yang, Chyan
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Abstract
Design for Testability (DFT) is receiving major emphasis in the very large scale integration design field due to increasing circuit complexity. The utility of the silicon compiler and its value to a system designer without extensive VLSI design experience is discussed. Two major techniques for DFT, Scanpath Design and Built-in Test Design, are implemented using the Genesil silicon compiler. The basic building block, the shiftable test latch, is described in random logic block form and parallel datapath form. Linear feedback shift registers used as random vector generators and signature analyzers are used in the Built-in Test design. An Automatic Test Generation program is used to provide a measure of fault coverage for the two DFT techniques. The appendix is a brief tutorial illustrating the use of the Genesil system's shiftable test latch in its different configurations
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This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.
URI
http://hdl.handle.net/10945/27087
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  • 1. Thesis and Dissertation Collection, all items

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    A methodology for producing and testing a Genesil Silicon Compiler designed VLSI chip which incorporates Design for Testability 

    Pooler, Brian Lee (Monterey, California: Naval Postgraduate School, 1990-09);
    Testability issues concerning the need for including Design for Testability (DFT) techniques in VLSI (Very Large Scale Integration) designs are discussed. Types of fault models, the use of fault simulation and the DFT ...
  • Thumbnail

    Implementation of residue code as a design for testability strategy using GENESIL Silicon Compiler 

    Lawson, John Ernest (Monterey, California: Naval Postgraduate School, 1990-12);
    This thesis describes the need for including design for testability in a VLSI chip design and provides information on implementing a DFT strategy using the GENESIL Silicon compiler. Two structured techniques of design for ...
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    A design of floating point FFT using Genesil Silicon Compiler. 

    Lu, Chung-Kuei. (Monterey, California. Naval Postgraduate School, 1991-06);
    The hardware of floating-point MULTIPLY, ADD, and SUBTRACT units are designed to support the multiplication, addition, and subtraction operation necessary in the Fast Fourier Transform (FFT). In this thesis, the IEEE ...
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