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dc.contributor.advisorLoomis, Herschel H., Jr.
dc.contributor.authorDavidson, John Carl
dc.dateMarch 1989
dc.date.accessioned2013-01-23T22:09:20Z
dc.date.available2013-01-23T22:09:20Z
dc.date.issued1989-03
dc.identifier.urihttp://hdl.handle.net/10945/27087
dc.description.abstractDesign for Testability (DFT) is receiving major emphasis in the very large scale integration design field due to increasing circuit complexity. The utility of the silicon compiler and its value to a system designer without extensive VLSI design experience is discussed. Two major techniques for DFT, Scanpath Design and Built-in Test Design, are implemented using the Genesil silicon compiler. The basic building block, the shiftable test latch, is described in random logic block form and parallel datapath form. Linear feedback shift registers used as random vector generators and signature analyzers are used in the Built-in Test design. An Automatic Test Generation program is used to provide a measure of fault coverage for the two DFT techniques. The appendix is a brief tutorial illustrating the use of the Genesil system's shiftable test latch in its different configurationsen_US
dc.description.urihttp://archive.org/details/implementationof1094527087
dc.format.extent115 p.en_US
dc.language.isoen_US
dc.publisherMonterey, California. Naval Postgraduate Schoolen_US
dc.rightsThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.en_US
dc.titleImplementation of a design for testability strategy using the Genesil silicon compileren_US
dc.typeThesisen_US
dc.contributor.secondreaderYang, Chyan
dc.contributor.corporateNaval Postgraduate School (U.S.)
dc.contributor.departmentDepartment of Electrical and Computer Engineering
dc.subject.authorDesign for testabilityen_US
dc.subject.authorScanpathen_US
dc.subject.authorBuilt-in testen_US
dc.subject.authorGenesil shiftable test latchen_US
dc.subject.authorSilicon compileren_US
dc.subject.authorLinear feedback shift registeren_US
dc.description.serviceLieutenant, United States Navyen_US
etd.thesisdegree.nameM.S. in Electrical Engineeringen_US
etd.thesisdegree.levelMastersen_US
etd.thesisdegree.disciplineElectrical Engineeringen_US
etd.thesisdegree.grantorNaval Postgraduate Schoolen_US
dc.description.distributionstatementApproved for public release; distribution is unlimited.


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