Design of a pipelined multiplier using a Silicon Compiler

Loading...
Thumbnail Image
Authors
Huber, Ronald Scott
Subjects
Silicon Compiler
Pipeline
Digital Multiplier
Advisors
Loomis, Herschel H.
Yang, Chyan
Date of Issue
1990-06
Date
June 1990
Publisher
Monterey, California: Naval Postgraduate School
Language
Abstract
This thesis describes the design methodology and the process of employing the GENESIL Silicon Compiler (GSC)(Version 7.1) in the layout of a pipelined multiplier, in 1.5 micron CMOS technology, using a parallel multiplier cell array. Additionally, background material on the theory of multiplication, as well as the concept and theory of pipelining are presented. The results revealed two practical limits of the GSC system which precluded achieving the high component density made possible by full custom manual CAD methods using graphic layout tools. Although the GSC system did not perform as desired in this study, it offers a viable alternative to the labor intensive, full custom, Very Large Scale Integration graphic layout tools in use today.
Type
Thesis
Description
Series/Report No
Department
Department of Electrical and Computer Engineering
Organization
Naval Postgraduate School (U.S.)
Identifiers
NPS Report Number
Sponsors
Funder
Format
xii, 94 p. ill.
Citation
Distribution Statement
Approved for public release; distribution is unlimited.
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.
Collections