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dc.contributor.advisorYang, Chyan
dc.contributor.authorYoon, Hee Byung.
dc.date.accessioned2013-02-15T23:31:27Z
dc.date.available2013-02-15T23:31:27Z
dc.date.issued1991-06
dc.identifier.urihttp://hdl.handle.net/10945/28171
dc.descriptionApproved for public release; distribution is unlimiteden_US
dc.description.abstractThe burst error is generated in digital communication networks by various unpredictable conditions, which occur at high error rates, for short durations, and can impact services. To completely describe a burst error one has to know the bit pattern. This is impossible in practice on working systems. Therefore, under the memoryless binary symmetric channel (MBSC) assumptions, the performance evaluation or estimation schemes for digital signal 1 (DS1) transmission systems carrying live traffic is an interesting and important problem. This study will present some analytical methods, leading to efficient detecting algorithms of burst error using cyclic redundancy check (CRC) code. The definition of burst error is introduced using three different models. Among the three burst error models, the mathematical model is used in this study. The probability density function, function(b) of burst error of length b is proposed. The performance of CRC-n codes is evaluated and analyzed using function(b) through the use of a computer simulation model within CRC block burst error. The simulation result shows that the mean block burst error tends to approach the pattern of the burst error which random bit errors generateen_US
dc.description.urihttp://archive.org/details/errorperformance00yoon
dc.format.extent66 p.;28 cm.en_US
dc.language.isoen_US
dc.publisherMonterey, California. Naval Postgraduate Schoolen_US
dc.titleThe error performance analysis over cyclic redundancy check codes.en_US
dc.typeThesisen_US
dc.contributor.secondreaderHa, Tri T.
dc.contributor.corporateNaval Postgraduate School
dc.contributor.schoolNaval Postgraduate School
dc.contributor.departmentElectrical Engineering
dc.contributor.departmentComputer Engineering
dc.subject.authorError Performance Analysis;en_US
dc.subject.authorCyclic Redundancy Check Codesen_US
dc.subject.authorCRC Block Burst Erroren_US
dc.description.serviceLT, Korean Navyen_US
etd.thesisdegree.nameM.S. in Electrical and Computer Engineeringen_US
etd.thesisdegree.levelMastersen_US
etd.thesisdegree.disciplineElectrical Engineering;Computer Engineeringen_US
etd.thesisdegree.grantorNaval Postgraduate Schoolen_US


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