Multiple-valued programmable logic array minimization by concurrent multiple and mixed simulated annealing.
Butler, Jon T.
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The process of finding a guaranteed minimal solution for a multiple-valued programmable logic expression requires an exhaustive search. Exhaustive search is not very realistic because of enormous computation time required to reach a solution. One of the heuristics to reduce this computation time and provide a nearminimal solution is simulated annealing. This thesis analyzes the use of loosely-coupled, course-grained parallel systems for simulated annealing. This approach involves the use of multiple processors where interprocess communication occurs only at the beginning and end of the process. In this study, the relationship between the quality of solution, measured by the number of products and computation time, and simulated annealing parameters are investigated. A simulated annealing experiment is also investigated where two types of moves are mixed. These approaches provide improvement in both the number of product terms and computation time.
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Yildirim, Cem; Yang, Chyan; Butler, Jon T. (1993-05);We analyze simulated annealing applied to multiple-valued programmable logic array (MVL PLA) design. Of spec@c interest is the use of parallel processors. We consider the use of loosely-coupled, coarse- grainedparallel ...
Oral, Sabri Onur (Monterey, California. Naval Postgraduate School, 1991-09);The process of finding an exact minimization for a multiple-valued logic (MVL) expression requires an extensive search and enormous computation time. One of the heuristics to reduce this computation time is the Neighborhood ...
Dueck, Gerhard W.; Earle, Robert C.; Tirumalai, Parthasarathy; Butler, Jon T. (1992-05);We propose a solution to the minimization problem of multiple-valued programmable logic arrays (PLA) that uses simulated annealing. The algorithm accepts a sum-ofproducts expression, divides and recombines the product ...