VHDL behavioral description of Discrete Cosine Transform in image compression.
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This thesis describes a VHSIC Hardware Description Language (VHDL) simulation of a hardware 8x8 Discrete Cosine Transform (DCT) which can be applied to image compression. A Top-Down Design approach is taken in the study, a discussion of DCT theory is presented, along with a description of the 1-D DCT circuit architecture and its simulation in VHDL. Results of the 2-D DCT simulation are included for two simple test patterns and verified by hand calculation, demonstrating the validity of the simulation. Shortcoming found in the simulation are described, together with suggestions for correcting them. In the future, the VHDL description of the 8 x 8 image block 2-D DCT can be further developed into structural and gate-level description, after which hardware circuit implement can occur.
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