A design of floating point FFT using Genesil Silicon Compiler.
MetadataShow full item record
The hardware of floating-point MULTIPLY, ADD, and SUBTRACT units are designed to support the multiplication, addition, and subtraction operation necessary in the Fast Fourier Transform (FFT). In this thesis, the IEEE floating-point standard is adopted and scaled down to 16 bits, but the exponent is an excess-8 number represented using radix-2. A 16 bit reduced word size floating-point arithematic unit for high speed signal analysis was implemented. The layout verification, functional simulation, and timing analysis of these units have been performed on the Genesil Silicon Compiler (GSC) system that was developed to overcome the shortcomings of the time consuming custom layout methods. The design of this thesis work can be used for further investigation of the high speed, pipelined floating-point arithmetic units.
RightsThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.
Showing items related by title, author, creator and subject.
Nagayama, Shinobu; Sasao, Tsutomu; Butler, Jon T. (2009);This paper proposes a design method for floating-point numerical function generators (NFGs) using multi-valued decision diagrams (MDDs). Our method applies to monotone elementary functions in which real values are converted ...
Kulke, Josef (Monterey, California. Naval Postgraduate School, 2022-04); NPS-SP-22-001This thesis covers parts of the development of a new open-source hardware Floating Spacecraft Simulator for teaching and research purposes, named MyDAS, standing for Mini Dynamic Autonomous Spacecraft Simulator. A Floating ...
Stuart, David Charles (Monterey, California: Naval Postgraduate School, 1990);A system of custom cell building blocks utilizing scaleable CMOS technology is decribed. The cells are design to support the high speed, pipelined addition, subtraction, and multiplication operations neccessary in a cyclic ...