A model for minimizing numeric function generator complexity and delay

Abstract

Numeric Function Generators (NFGs) have allowed computation of difficult mathematical functions in less time and with less hardware than commonly employed methods. They compute piecewise linear (or quadratic) approximations that represent the value of the original function for a given input value. The domain of the NFG is divided into enough segments such that the approximation is within the required error to the actual value of the function. The linear (or quadratic) approximation varies for each segment. The overall hardware complexity and propagation delay depend on the number of segments required, the arithmetic devices used to approximate the function, and the number of bits used to represent the numbers being calculated. This thesis develops an accurate method to quantify hardware utilization and propagation delay for various NFG configurations implemented on Field-Programmable Gate Arrays (FPGAs). The algorithms and estimation techniques apply to different NFG architectures and to different mathematical functions. This thesis compares hardware utilization and propagation delay for various NFG architectures, mathematical functions, word widths, and segmentation methods. It shows when a quadratic NFG requires less hardware and when it has a longer delay than its linear NFG counterpart for various functions. It also establishes a criterion for when non-uniform segmentation is beneficial for any function, based on the size of the NFG. The findings in this thesis show that NFGs with non-uniform segmentation generally require more hardware and almost always have longer delays than NFGs with uniform segmentation. They also show that quadratic NFGs required less hardware and have shorter delays as the size of the NFG gets larger.