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dc.contributor.advisorFouts, Douglas J.
dc.contributor.authorAndreasen, Peter Allen
dc.dateDecember 1995
dc.date.accessioned2013-04-29T22:48:54Z
dc.date.available2013-04-29T22:48:54Z
dc.date.issued1995-12
dc.identifier.urihttp://hdl.handle.net/10945/31269
dc.description.abstractThis thesis proposes a new Gallium Arsenide (GaAs) Dynamic Random Access Memory (DRAM) storage cell design based on an n-type, depletion mode diode and evaluates an Emitter-Coupled Logic (ECL) based test platform. The depletion mode diode storage cell exhibits improved charge storage and maintenance characteristics when compared with a previously designed capacitor- based storage cell. Power requirements of the diode-based cell are marginally increased. The modularity of the new diode-based design produces impressive improvements in Very Large Scale Integration (VLSI) layout. The smaller design promises a higher degree of memory cell integration for future GaAs DRAM applications. The ECL test platform provides DATA, READ, WRITE, REFRESH and CLOCK signals as well as power and ground requirements for a GaAs DRAM chip in a 132-pin package. All testbench systems are tested and prove functional but CLOCK and REFRESH signal integrity suffer from noise and connector losses above 100 MHz. Ultimately, the ECL test platform failed to test the existing GaAs DRAM due to pin-out incompatibility. Recommendations for future test platforms are discussed along with suggestions for incorporation of the diode-based memory cell in new DRAM designs. jg p2en_US
dc.description.urihttp://archive.org/details/galliumrsenidedr1094531269
dc.format.extent89 p.en_US
dc.language.isoen_US
dc.publisherMonterey, California. Naval Postgraduate Schoolen_US
dc.rightsThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.en_US
dc.titleGallium arsenide DRAM memory cell design and evaluation of test methodsen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical Engineering
dc.description.funderNAen_US
dc.description.recognitionNAen_US
dc.description.serviceU.S. Navy (U.S.N.) author.en_US
etd.thesisdegree.nameM.S. in Electrical Engineeringen_US
etd.thesisdegree.levelMastersen_US
etd.thesisdegree.disciplineElectrical Engineeringen_US
etd.thesisdegree.grantorNaval Postgraduate Schoolen_US


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