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dc.contributor.advisorLoomis, Herschel H., Jr.
dc.contributor.authorBernstein, Raymond F.
dc.dateDecember 1995
dc.date.accessioned2013-04-29T22:49:04Z
dc.date.available2013-04-29T22:49:04Z
dc.date.issued1995-12
dc.identifier.urihttp://hdl.handle.net/10945/31275
dc.description.abstractThis work describes a scaleable, high performance, pipelined, vector processor architecture. Special emphasis is placed on performing fast Fourier transforms with mixed-radix butterfly operations. The initial motivation for the architecture was the computation of cyclostationary algorithms. However, the resulting architecture is capable of general purpose vector processing as well. A major factor affecting the performance of the architecture is the memory system design. The use of pipelining techniques, coupled with vector processing, places a substantial burden on the memory system performance. The memory design is based on an interleaved memory philosophy with a buffering technique referred to as split transaction memory (STM). A crucial aspect of the memory design is the memory decoding scheme. A design methodology is described for the specification of permutation matrices that yield near optimal performance for the memory system. Another important aspect of this work is the development of a software based simulator that allows a STM to be specified. The simulator, operating at the register transfer level, emulates the processing of an address stream by STM and records the events for post-processing. The STM simulator was used to evaluate three types of vector processing address patterns: constant stride, constant geometry radix-r butterfly, and digit reversed. A random address pattern was also analyzed in the context of general-purpose computing. STM simulation verified the near-optimal performance of the STM.en_US
dc.description.urihttp://archive.org/details/apipelinedvector1094531275
dc.format.extent254 p.en_US
dc.language.isoen_US
dc.publisherMonterey, California. Naval Postgraduate Schoolen_US
dc.rightsThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.en_US
dc.titleA pipelined vector processor and memory architecture for cyclostationary processingen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical Engineering
dc.description.funderNAen_US
dc.description.recognitionNAen_US
dc.description.serviceNaval Postgraduate School author.en_US
etd.thesisdegree.namePh.D. in Electrical Engineeringen_US
etd.thesisdegree.levelDoctoralen_US
etd.thesisdegree.disciplineElectrical Engineeringen_US
etd.thesisdegree.grantorNaval Postgraduate Schoolen_US


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