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dc.contributor.advisorSherif Michael
dc.contributor.authorChunda, Jaime P.
dc.dateJune 1995
dc.date.accessioned2013-04-29T22:50:31Z
dc.date.available2013-04-29T22:50:31Z
dc.date.issued1995-06
dc.identifier.urihttp://hdl.handle.net/10945/31417
dc.description.abstractIn this research, a low voltage BiCMOS operational amplifier was built using parasitic bipolar transistors in bulk CMOS technology. Designed and analyzed using PSPICE circuit simulation software, the amplifier achieves a gain bandwidth product of 20.24 MHz with power supply voltages of +/- 2.5 V. The simulation proved that the BiCMOS amplifier will operate with power supplies as low as +/- 0.6 V. Using MAGIC VLSI software, a layout of the amplifier was made for eventual fabrication in the MOSIS 2.0 m CMOS process.en_US
dc.description.urihttp://archive.org/details/lowvoltageoperat1094531417
dc.format.extent87 p.en_US
dc.language.isoen_US
dc.publisherMonterey, California. Naval Postgraduate Schoolen_US
dc.rightsThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.en_US
dc.titleLow voltage operational amplifier using parasitic bipolar transistors in CMOSen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical Engineering
dc.description.funderNAen_US
dc.description.recognitionNAen_US
dc.description.serviceU.S. Navy (U.S.N.) author.en_US
etd.thesisdegree.nameM.S. in Electrical Engineeringen_US
etd.thesisdegree.levelMastersen_US
etd.thesisdegree.disciplineElectrical Engineeringen_US
etd.thesisdegree.grantorNaval Postgraduate Schoolen_US


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