Tools for binary decision diagram analysis
dc.contributor.advisor | Butler, Jon T. | |
dc.contributor.author | Ang, Kwee Hua | |
dc.date | March 1995 | |
dc.date.accessioned | 2013-04-29T22:51:14Z | |
dc.date.available | 2013-04-29T22:51:14Z | |
dc.date.issued | 1995-03 | |
dc.identifier.uri | https://hdl.handle.net/10945/31515 | |
dc.description.abstract | The Binary Decision Diagram (BDD) is a very useful representation in the design and verification of switching functions. This is due to to its compactness, where size is measured by the number of nodes. In the implementation of logic circuits, connection of sub-functions is by means of pass transistors. The delay time for the interconnections is often larger than the delay of the decision logic. For that reason, crossings are often more expensive than logic. Planar Binary Decision Diagrams are therefore desirable in implementing logic circuits. This paper presents a method for finding a planar Ordered Binary Decision Diagram (OBDD) for threshold functions. The program that implements the algorithm is written in Borland C++. A special case of Fibonacci threshold function having up to 9 variables is analyzed. It is shown that Fibonacci functions having up to 9 variables have planar OBDD. With this program, the characteristics of other threshold functions are developed. | en_US |
dc.description.uri | http://archive.org/details/toolsforbinaryde1094531515 | |
dc.format.extent | 81 p. | en_US |
dc.language.iso | en_US | |
dc.publisher | Monterey, California. Naval Postgraduate School | en_US |
dc.rights | This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States. | en_US |
dc.title | Tools for binary decision diagram analysis | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | Electrical Engineering | |
dc.description.funder | NA | en_US |
dc.description.recognition | NA | en_US |
dc.description.service | Republic of Singapore Airforce author. | en_US |
etd.thesisdegree.name | M.S. in Electrical Engineering | en_US |
etd.thesisdegree.level | Masters | en_US |
etd.thesisdegree.discipline | Electrical Engineering | en_US |
etd.thesisdegree.grantor | Naval Postgraduate School | en_US |
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