RESEARCH, DEVELOPMENT AND TESTING OF A FAULT-TOLERANT FPGA-BASED SEQUENCER FOR CUBESAT LAUNCHING APPLICATIONS

Abstract

This thesis concerns various means of implementing fault tolerance in logic for use in a general payload processor design. The first specific application of this research is a sequencer developed for deploying CubeSats. The sequencer shall be capable of the timing and accurate deployment of multiple CubeSats from a host spacecraft and shall have the capability for quick reconfiguration prior to launch. This research considers a variety of hardware for suitability toward sequencer construction; field programmable gate arrays (FPGAs) are chosen as the primary device. The design further evolves to selection of the Actel ProASIC3 series of FPGAs. Initial logic test configurations are implemented on a development kit with analysis of results provided. Fault-tolerant techniques are compared with a set of experiments to determine optimum resource utilization and timing schemes. Triple modular redundancy (TMR) is selected as the technique for fault-tolerant logic implementation in the sequencer. Preliminary test boards are built via schematic design and printed circuit board layout. The manufacturing, integration and testing of the ProASIC3 Test Board is fully discussed. A follow-on flight prototype board is designed with more extensive hardware allowing for implementation of fault-tolerant techniques and future growth capability. Recommendations for future work are discussed.