A methodology for producing and testing a Genesil Silicon Compiler designed VLSI chip which incorporates Design for Testability
Pooler, Brian Lee
Loomis, Herschel H.
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Testability issues concerning the need for including Design for Testability (DFT) techniques in VLSI (Very Large Scale Integration) designs are discussed. Types of fault models, the use of fault simulation and the DFT techniques of Scan Path and Built in Test are described. An engineering methodology that uses the Genesil Silicon Compiler to produce a VLSI design, DFT-CHIP, which utilizes the DFT Scan Path technique is presented. Included are the procedures for using Genesil's simulation, timing analysis and automatic test generation features. The steps taken to fabricate the DFT-CHIP design through MOSIS are discussed. The methodology used to test the fabricated DFT- CHIP design on the Tektronix DAS 9100 tester is described. Appendix A and Appendix B provide copies of the Genesil check functions written for use during simulation on the DFT-CHIP design. Appendix C specifies the Genesil timing information for the DFT-CHIP design. Appendix D lists the conversion program which translates Genesil produced test vector files to the file format used during testing on the Tektronix tester.
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