Security Checkers: Detecting Processor Malicious Inclusions at Runtime
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Authors
Bilzor, Michael
Huffmire, Ted
Irvine, Cynthia
Levin, Tim
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Date of Issue
2011
Date
2011
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Abstract
To counter the growing threat of malicious subversions
to the design of a microprocessor, there is a great need for
simple, automated methods for detecting such malevolent changes.
Based on the adoption of the Property Specification Language
(PSL) for behavioral verification, and the advent of tools for
automatically generating synthesizable hardware design language
(HDL) constructs for verifying a PSL assertion, we propose a new
method called Security Checkers, which uses security-focused PSL
assertions to create hardware design units for detecting malicious
inclusions at runtime.
We describe the process flow for creating Security Checkers and
demonstrate by example how they can be used to detect malicious
inclusions in a processor design. Because the checkers can be
used in simulation, FPGA emulation, or as part of a fabricated
design, we illustrate how this technique can be used to detect
malicious inclusions over a much broader segment of the
Type
Conference Paper
Poster
Poster
Description
In Hardware-Oriented Security and Trust (HOST), 2011 IEEE International Symposium on, 2011, pp. 34-39.
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This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.