Decimation of encoding errors in an optimum SNS 2 [mu] low-noise CMOS ADC
Schafer, Jeffrey L.
Pace, Phillip E.
Fouts, Douglas J.
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Significant research in high performance analog-to-digital converters (ADCs) has been directed at retaining part of the high-speed flash ADC architecture, while reducing the total number of comparators in the circuit. The symmetrical number system (SNS) can he used to preprocess the analog input signal, reducing the number of comparators and thus reducing the chip area and Power consumption of the ADC. This thesis examines the issue of encoding errors that result when the separate channels m sub i are brought together to derive the input analog voltage. The Very Large Scale Integrated (VLSI) design for the comparators, error checking circuits and Programmable Logic Arrays (PLAs) use the Orbit 2 Micron CMOS N-well double-metal, double-poly fabrication process. Steady state transfer functions are shown which detail encoding errors that occur when the folded input samples lie at one of the code transition Points. To discard the encoding errors that occur, a decimation band is constructed at each transition Point The effectiveness of the decimation band in eliminating the encoding errors and the linearity error is quantified. An Application Specific Integrated Circuit (ASIC) is designed.
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