Design techniques for the prevention of radiation-induced latch-up in bulk CMOS processes
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Authors
Madsen, Anne
Subjects
Advisors
Fouts, Douglas J.
Date of Issue
1995-09
Date
September 1995
Publisher
Monterey, California. Naval Postgraduate School
Language
en_US
Abstract
Design and layout techniques are described for preventing radiation- induced latch-up in CMOS VLSI ICs using non-radiation hardened bulk CMOS processes. Such ICs are suitable for use in satellites and other systems where proper operation in a radiation environment is critical in the short term, but where long-term survivability is of less importance. Basic radiation effects are discussed, emphasizing areas where bulk CMOS processes are most susceptible. Two custom CMOS VLSI ICs are designed to demonstrate the described techniques. Test plans are developed for testing and evaluating the described ICs using the investigative techniques.
Type
Thesis
Description
Series/Report No
Department
Electrical Engineering
Organization
Identifiers
NPS Report Number
Sponsors
Funder
NA
Format
75 p.
Citation
Distribution Statement
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.