Design techniques for the prevention of radiation-induced latch-up in bulk CMOS processes

Abstract

Design and layout techniques are described for preventing radiation- induced latch-up in CMOS VLSI ICs using non-radiation hardened bulk CMOS processes. Such ICs are suitable for use in satellites and other systems where proper operation in a radiation environment is critical in the short term, but where long-term survivability is of less importance. Basic radiation effects are discussed, emphasizing areas where bulk CMOS processes are most susceptible. Two custom CMOS VLSI ICs are designed to demonstrate the described techniques. Test plans are developed for testing and evaluating the described ICs using the investigative techniques.