Naval Postgraduate School
Analysis of input and output configurations for use in four-valued programmable logic arrays
But_Ker_IEE1987.pdf (1.059Mb)Abstract
As in binary, a multiple-valued programmable logic array (PLA) realises a sum-of-products, expression specified by the user. However, in multiple-valued logic, there are many more operations than in binary, and an important question is the choice of operations with provides the greatest number of functions for a given chip area. In this paper, we analyse various PLA configurations using operations realised in the peristaltic multiple-valued CCD technology. We compare a multiple-valued CCD PLA implementation with four other proposed designs and show that there is a significant different in chip area required to realise the same set of functions. The basis of comparison is the set of 4-valued unary functions.
Description
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.
Proceedings of the IEE-E: Computers and Digital Techniques, Vol. 134, No. 4, pp. 168-176, July 1987
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