A minimization algorithm for non-concurrent PLA's
Due_But_IJE1992.pdf (357.4Kb)Abstract
In the design of certain self-checking programmable logic arrays (PLAs), at most one line is activated in the AND plane, such as PLAs are termed non-concurrent. A heuristic algorithm for the minimization of non-concurrent PLAs is presented. It operates on two adjacent cubes, replacing them by one, two, and sometimes more than two cubes. The algorithm produces the best solutions known so far.
Description
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.
International Journal of Electronics, Vol. 73, No. 6, Dec. 1992, pp. 1113-1119
Collections
Related items
Showing items related by title, author, creator and subject.
-
Decomposition recovery extension to the Computer Aided Prototyping System (CAPS) change-merge tool.
(Monterey, California. Naval Postgraduate School, 1997-09);A promising use of Computer Aided Prototyping System (CAPS) is to support concurrent design. Key to success in this context is the ability to automatically and reliably combine and integrate the prototypes produced in ... -
The minimization of multiple valued logic expressions using parallel processors
(Monterey, California. Naval Postgraduate School, 1991-09);The process of finding an exact minimization for a multiple-valued logic (MVL) expression requires an extensive search and enormous computation time. One of the heuristics to reduce this computation time is the Neighborhood ... -
Geometry-of-fire tracking algorithm for direct-fire weapon systems
(Monterey, California: Naval Postgraduate School, 2015-09);The continuous cycle for validating geometry of fires on a battlefield impedes momentum. A force that can decide and act quicker than the enemy has an advantage. The goal of this thesis is to provide dismounted infantry ...
