A minimization algorithm for non-concurrent PLA's
Dueck, Gerhard W.
Butler, Jon T.
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In the design of certain self-checking programmable logic arrays (PLAs), at most one line is activated in the AND plane, such as PLAs are termed non-concurrent. A heuristic algorithm for the minimization of non-concurrent PLAs is presented. It operates on two adjacent cubes, replacing them by one, two, and sometimes more than two cubes. The algorithm produces the best solutions known so far.
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.International Journal of Electronics, Vol. 73, No. 6, Dec. 1992, pp. 1113-1119
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