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dc.contributor.authorSchueller, Kriss A.
dc.contributor.authorButler, Jon T.
dc.dateOctober 8, 1995
dc.date.accessioned2013-09-03T22:30:08Z
dc.date.available2013-09-03T22:30:08Z
dc.date.issued1995-10
dc.identifier.citationA preliminary version of this manuscript appeared in the Proceedings of the 28th Annual Allerton Conference on Communication, Control, and Computing, October 1990.
dc.identifier.urihttp://hdl.handle.net/10945/35762
dc.descriptionThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.en_US
dc.descriptionProceedings of the 28th Annual Allerton Conference on Communication, Control, and Computing, Sept. 1990, regular (full)paper, pp. 948-957 (Unrefereed)1989en_US
dc.description.abstractWe analyze the computational complexity of the cost-table approach to designing multiple alued logic circuits that is applicable to I L, CCD’s, current-mode CMOS, and RTD’s. We s 2 how that this approach is NP-complete. An efficient algorithm is shown for finding the exact I minimal realization of a given function by a given cost-table.en_US
dc.titleComplexity analysis of the cost-table approach to the design of multiple-valued logic circuitsen_US
dc.typeArticleen_US
dc.contributor.departmentDepartment of Electrical and Computer Engineering
dc.subject.authorcomputational complexityen_US
dc.subject.authorcost-tableen_US
dc.subject.authorcost functionen_US
dc.subject.authorlogic designen_US
dc.subject.authorminimizationen_US
dc.subject.authormultiple-valued logicen_US
dc.subject.authorNP-completeen_US
dc.subject.authorsynthesisen_US


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