Complexity analysis of the cost-table approach to the design of multiple-valued logic circuits
Sch_But_IEEETC1997.pdf (127.2Kb)Abstract
—We analyze the computational complexity of the cost-table
approach to designing multiple-valued logic circuits that is applicable to
I
2
L, CCDs, current-mode CMOS, and RTDs. We show that this
approach is NP-complete. An efficient algorithm is shown for finding
the exact minimal realization of a given function by a given cost-table.
Description
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.
IEEE Transactions on Computers, February 1997, pp. 205-209
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