Multiple-valued PLA minimization by concurrent multiple and mixed simulated annealing

Abstract

We analyze simulated annealing applied to multiple-valued programmable logic array (MVL PLA) design. Of spec@c interest is the use of parallel processors. We consider the use of loosely-coupled, coarse- grainedparallel systems, and study the relationship between the quality of the solution and computation time, on the one hand, and simulated annealing parameters, start temperature, cooling rate, etc., on the other. We also investigate simulated annealing where there is a mixture of move types. The mixed move approach provides improvement in both the number of product terms and computation time.