Numerical function generators using LUT cascades

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Author
Sasao, Tsutomu
Nagayama, Shinobu
Butler, Jon T.
Date
2007-06Metadata
Show full item recordAbstract
This paper proposes an architecture and a synthesis method for high-speed computation of fixed-point numerical functions
such as trigonometric, logarithmic, sigmoidal, square root, and combinations of these functions. Our architecture is based on the
lookup table (LUT) cascade, which results in a significant reduction in circuit complexity compared to traditional approaches. This is
suitable for automatic synthesis and we show a synthesis method that converts a Matlab-like specification into an LUT cascade design.
Experimental results show the efficiency of our approach as implemented on a field-programmable gate array (FPGA).
Description
IEEE Transactions on Computers, Vol.56, No.6, June 2007, pp.826-838.
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.
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