Numerical function generators using LUT cascades

Sasao, Tsutomu; Nagayama, Shinobu; Butler, Jon T.

dc.contributor.author	Sasao, Tsutomu
dc.contributor.author	Nagayama, Shinobu
dc.contributor.author	Butler, Jon T.
dc.date	2007-06
dc.date.accessioned	2013-09-03T22:33:00Z
dc.date.available	2013-09-03T22:33:00Z
dc.date.issued	2007-06
dc.identifier.citation	T. Sasao, S. Nagayama and J. T. Butler, "Numerical function generators using LUT cascades," IEEE Transactions on Computers, Vol.56, No.6, June 2007, pp.826-838.
dc.identifier.uri	https://hdl.handle.net/10945/35828
dc.description	IEEE Transactions on Computers, Vol.56, No.6, June 2007, pp.826-838.	en_US
dc.description	This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.	en_US
dc.description.abstract	This paper proposes an architecture and a synthesis method for high-speed computation of fixed-point numerical functions such as trigonometric, logarithmic, sigmoidal, square root, and combinations of these functions. Our architecture is based on the lookup table (LUT) cascade, which results in a significant reduction in circuit complexity compared to traditional approaches. This is suitable for automatic synthesis and we show a synthesis method that converts a Matlab-like specification into an LUT cascade design. Experimental results show the efficiency of our approach as implemented on a field-programmable gate array (FPGA).	en_US
dc.title	Numerical function generators using LUT cascades	en_US
dc.type	Article	en_US
dc.contributor.department	Department of Electrical and Computer Engineering
dc.subject.author	LUT cascades	en_US
dc.subject.author	numerical function generators (NFGs)	en_US
dc.subject.author	nonuniform segmentation	en_US
dc.subject.author	automatic synthesis	en_US
dc.subject.author	FPGA implementation	en_US