On the average path length in decision diagrams of multiple-valued functions
Abstract
We consider the path length in decision diagrams
for multiple-valued functions. This is an important
measure of a decision diagram, since this models the
time needed to evaluate the function. We consider the path length in decision diagrams
for multiple-valued functions. This is an important
measure of a decision diagram, since this models the
time needed to evaluate the function. We consider the path length in decision diagrams
for multiple-valued functions. This is an important
measure of a decision diagram, since this models the
time needed to evaluate the function. We consider the path length in decision diagrams
for multiple-valued functions. This is an important
measure of a decision diagram, since this models the
time needed to evaluate the function...
Description
33rd International Symposium on Multiple-Valued Logic, Tokyo, May 16-19, 2003. pp.383-390.
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.
Collections
Related items
Showing items related by title, author, creator and subject.
-
Average path length of binary decision diagrams
Sasao, Tsutomu; Matsuura, Munehiro; Butler, Jon T. (2005-09);The traditional problem in binary decision diagrams (BDDs) has been to minimize the number of nodes since this reduces the memory needed to store the BDD. Recently, a new problem has emerged: minimizing the average path ... -
Planarity in ROMDD's of multiple-valued symmetric functions
Nowlin, Jeffrey L. (Monterey, California. Naval Postgraduate School, 1996-03);An important consideration in the design of digital circuits is delay. A major source of delay in VLSI is interconnect. Crossings among interconnect require via's which cause resistance and additional delay. This thesis ... -
Planar Decision Diagrams for Multiple-Valued Functions
Sasao, Tsutomu; Butler, Jon T. (1996);In VLSI, crossings of interconnect occupy space and cause delay. Therefore, there is significant benefit to planar circuits. We propose the use of planar multiple-valued decision diagrams for produce planar multiple-valued ...