A quaternary decision diagram machine and the optimization of its code
| dc.contributor.author | Sasao, Tsutomu | |
| dc.contributor.author | Nakahara, Hiroki | |
| dc.contributor.author | Matsuura, Munehiro | |
| dc.contributor.author | Kawamura, Yoshifumi | |
| dc.contributor.author | Butler, Jon T. | |
| dc.date | May 21-23, 2009 | |
| dc.date.accessioned | 2013-09-03T22:33:02Z | |
| dc.date.available | 2013-09-03T22:33:02Z | |
| dc.date.issued | 2009-05 | |
| dc.identifier.citation | T. Sasao, H. Nakahara, M. Matsuura, Y. Kawamura, and J.T. Butler, "A quaternary decision diagram machine and the optimization of its code," 39th International Symposium on Multiple-Valued Logic (ISMVL 2009), May 21-23, 2009,pp.362-369. | |
| dc.identifier.uri | http://hdl.handle.net/10945/35839 | |
| dc.description | 39th International Symposium on Multiple-Valued Logic (ISMVL 2009), May 21-23, 2009,pp.362-369. | en_US |
| dc.description | This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted. | en_US |
| dc.description.abstract | We show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed improvement of 1.28-2.02 times when QDDs are chosen. We consider 1-and 2-address BDD machines, and 3- and 4-address QDD machines, and we show a method to minimize the number of instructions. | en_US |
| dc.title | A quaternary decision diagram machine and the optimization of its code | en_US |
| dc.type | Article | en_US |
| dc.contributor.department | Department of Electrical and Computer Engineering |
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