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dc.contributor.authorSasao, Tsutomu
dc.contributor.authorNakahara, Hiroki
dc.contributor.authorMatsuura, Munehiro
dc.contributor.authorKawamura, Yoshifumi
dc.contributor.authorButler, Jon T.
dc.dateMay 21-23, 2009
dc.date.accessioned2013-09-03T22:33:02Z
dc.date.available2013-09-03T22:33:02Z
dc.date.issued2009-05
dc.identifier.citationT. Sasao, H. Nakahara, M. Matsuura, Y. Kawamura, and J.T. Butler, "A quaternary decision diagram machine and the optimization of its code," 39th International Symposium on Multiple-Valued Logic (ISMVL 2009), May 21-23, 2009,pp.362-369.
dc.identifier.urihttp://hdl.handle.net/10945/35839
dc.description39th International Symposium on Multiple-Valued Logic (ISMVL 2009), May 21-23, 2009,pp.362-369.en_US
dc.descriptionThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.en_US
dc.description.abstractWe show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed improvement of 1.28-2.02 times when QDDs are chosen. We consider 1-and 2-address BDD machines, and 3- and 4-address QDD machines, and we show a method to minimize the number of instructions.en_US
dc.titleA quaternary decision diagram machine and the optimization of its codeen_US
dc.typeArticleen_US
dc.contributor.departmentDepartment of Electrical and Computer Engineering


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