On the design of LPM address generators using multiple LUT Cascades on FPGAs
Butler, Jon T.
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We propose the multiple LUT cascade as a means to conﬁgure an n-input LPM (Longest Preﬁx Match) address generator commonly used in routers to determine the output port given an address. The LPM address generator accepts n-bit addresses which it matches against k stored preﬁxes. We implement our design on a Xilinx Spartan-3 FPGA for n = 32 and k = 504 ∼ 511. Also, we compare our design to a Xilinx proprietary TCAM (ternary content-addressable memory) design and to another design we propose as a likely solution to this problem. Our best multiple LUT cascade implementation has 5.17 times more throughput, 40.71 times more throughput/area and is 2.97 times more eﬃcient in terms of area-delay product than Xilinx’s proprietary design, but its area is only 15% of Xilinx’s design. Furthermore, we derive a method to determine the optimum conﬁguration of the multiple LUT cascade on an FPGA.
International Journal of Electronics, Vol. 94, Issue 5, May 2007, pp.451-467,This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.
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