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dc.contributor.authorJiexin Zhang
dc.contributor.authorDong, Jin Song
dc.contributor.authorYang Liu
dc.contributor.authorAuguston, Mikhail
dc.contributor.authorJun Sun
dc.dateDecember 4 – 7, 2012
dc.date.accessioned2013-09-13T16:08:37Z
dc.date.available2013-09-13T16:08:37Z
dc.date.issued2013-09-13
dc.identifier.citationJiexin Zhang, Yang Liu, Auguston, Mikhail, Jun Sun and Jin Song Dong, “Using Monterey Phoenix to Formalize and Verify System Architectures”, 19th Asia-Pacific Software Engineering Conference APSEC 2012, December 4 – 7, 2012, Hong Kong
dc.identifier.urihttp://hdl.handle.net/10945/36351
dc.description19th Asia-Pacific Software Engineering Conference APSEC 2012, December 4 – 7, 2012, Hong Kongen_US
dc.description.abstractModeling and analyzing software architectures are useful for helping to understand the system structures and facilitate proper implementation of user requirements. Despite its importance in the software engineering practice, the lack of formal description and verification support hinders the development of quality architectural models. In this work, we develop an approach for modeling and verifying software architectures specified using Monterey Phoenix (MP) architecture description language. Firstly, we formalize the syntax and operational semantics for MP. This language is capable of modeling system and environment behaviors based on event traces, as well as supporting different architecture composition operations and views. Secondly, a dedicated model checker for MP is developed based on PAT verification framework. Finally, several case studies are presented to evaluate the usability and effectiveness of our approach.en_US
dc.rightsThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.en_US
dc.titleUsing Monterey Phoenix to Formalize and Verify System Architecturesen_US
dc.contributor.departmentComputer Science Department


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