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dc.contributor.authorFouts, Douglas J.
dc.contributor.authorMcKerrow, Gary R.
dc.contributor.authorLum, Gary K.
dc.contributor.authorNoe, Sidney S.
dc.contributor.authorLambley, Andrew S.
dc.date.accessioned2014-01-29T18:17:49Z
dc.date.available2014-01-29T18:17:49Z
dc.date.issued2000
dc.identifier.citationMicrelectronics Reliability, 40 (2000) pp. 955-963
dc.identifier.urihttp://hdl.handle.net/10945/38488
dc.description.abstractCMOS integrated circuits (ICs) operating in space or other radiation environments can suffer from three different reliability problems due to the radiation: total dose effects, dose rate effects, and single event effects. The two most significant total-dose reliability problems are subthreshold, gat, end-around leakage current and threshold voltage shift. This article documents the theory, design, implementation, and testing of new, second-layer polysilicon structures that can compensate for radiation-induced, subthreshold, gate, end-around, leakage current. Second-layer polysilicon is available in many commercial, bulk CMOS processes and is normally used for floating-gate devices, such as EEPROMs and FPLAs, and charge-coupled devices such as CCD focal plan arrays. The use of the described structures in CMOS ICs would allow radiation tolerant ICs to be fabricated with commercial, bulk CMOS processors, greatly reducing manufacturing costs when compared to the cost of fabricating ICs on dedicated, radiation-hardened process lines.en_US
dc.publisherElsevieren_US
dc.rightsThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.en_US
dc.titleSecond-layer polysilicon structures for gate end-around leakage-current compensation in bulk CMOS ICsen_US
dc.typeArticleen_US
dc.contributor.corporateNaval Postgraduate School
dc.contributor.departmentDepartment of Electrical and Computer Engineering


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