An analog preprocessing architecture for high-speed analog-to-digital conversion
Esparza, Jorge A.
Fouts, Douglas J.
Pace, Phillip E.
MetadataShow full item record
This thesis investigates the feasibility of implementing an analog- to-digital converter (ADC) based on a new symmetrical number system (SNS). This preprocessing architecture decomposes the analog amplitude analyzing function of an ADC into a number of sub-operations (moduli). Each sub-operation folds the analog signal with a folding period proportional to the value of the modulus. Through the use of the SNS encoding and recombining the results of the sub- operations, a definitive performance enhancement is achieved. The number of comparators required is reduced considerably, allowing more bandwidth to be used in the folding circuits. The overall design effort demonstrates a 9-bit design with a total of 23 comparators. SPICE simulations are developed and the performance demonstrated. Also identified are the areas in which further research is required.
Approved for public release; distribution is unlimited.
Showing items related by title, author, creator and subject.
Pace, Phillip E.; Leino, Richard E.; Styer, David (The United States of America as represented by the Secretary of the Navy, Washington, DC (US), 2000-02-29);An antenna receives an analog waveform and an analog signal indicative of the amplitude and frequency of the analog waveform. The analog signal is processed in a plurality of parallel digital processing channels each arranged ...
Carr, Richard D. (Monterey, California. Naval Postgraduate School, 1994-12);Significant research in high performance analog-to-digital converters (ADCs) has been directed at retaining part of the high-speed flash ADC architecture, while reducing the total number of comparators in the circuit. The ...
Anderson, Thomas McArthur (Massachusetts Institute of Technology, 1963);An Analog Electro-Optical Multiplier, a simple and compact buiid state device with no moving parts, has been designed, constructed, and tested. Functionally, this device is the direct analog of the familiar servo-multiplier, ...