Publication:
Performance of high-reliability space-qualified processors implementing software defined radios

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Authors
Loomis, Herschel H., Jr.
Dinolt, George W.
Kragh, Frank E.
Subjects
Fault-tolerant Processors
Radiation-Hard Processors
FFTW
Software Defined Radio
SDR
Space-Qualified Processors
Advisors
Date of Issue
2014-03
Date
March 2014
Publisher
Monterey, California. Naval Postgraduate School
Language
Abstract
This report provides results of a study of the application to software-defined radios (SDR) of the Maestro 49-tile Radiation-Hard-by-Design multi-processor chip developed by Boeing Corporation for the U.S. Government using DARPA-developed radiation-hard chip technology. The heart of the pipeline SDR architecture is an implementation of single-precision floating-point pipeline FFT. The details of the software architecture to achieve the pipeline operation are presented. The performance of N-point FFTs for N = 128, 256, 512, 1024, and 2048 is reported as number of processor tiles is increased. Maximum FFT throughput achieved for a 2048-point FFT is 27 million samples per second when 20 of the 49 available tiles are used for separate FFT blocks, one tile is used for input data distribution, and one tile is used for output data collection. The performance of the complete SDR is projected based upon the FFT experiments.
Type
Technical Report
Software
Description
Includes supplementary material. (Software)
The software code that supports this Technical Report may be accessed with this record.
Series/Report No
Department
Electrical and Computer Engineering
Identifiers
NPS Report Number
NPS-EC-14-002
Sponsors
Funder
Secretary of the Air Force
Format
Citation
Distribution Statement
Approved for public release; distribution is unlimited.
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.