Trustworthy system development through high-level synthesis
dc.contributor.advisor | Huffmire, Theodore | |
dc.contributor.author | Patterson, Isaac | |
dc.date | Sep-14 | |
dc.date.accessioned | 2014-12-05T20:10:43Z | |
dc.date.available | 2014-12-05T20:10:43Z | |
dc.date.issued | 2014-09 | |
dc.identifier.uri | http://hdl.handle.net/10945/43974 | |
dc.description.abstract | Major processor manufacturers have embraced the high-level synthesis (HLS) design philosophy. HLS offers the potential to explore the design space of electronic circuits and systems more efficiently than traditional methods. In this thesis, we investigate the ap-plication of HLS to hardware-oriented security and trust by developing a model of a simple 16-bit Central Processing Unit in the SystemC modeling language. We enhanced our processor with a simple security mechanism that enforces a memory integrity policy. The integrity policy allows a region of the program labeled as trustworthy to modify any address in data memory, but another region of the program labeled as untrustworthy is restricted to only being able to modify a specific region of data memory. Our timing results show that adding the integrity policy enforcement mechanism has a negligible effect on overall system performance. | en_US |
dc.description.uri | http://archive.org/details/trustworthysyste1094543974 | |
dc.publisher | Monterey, California: Naval Postgraduate School | en_US |
dc.rights | This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States. | en_US |
dc.title | Trustworthy system development through high-level synthesis | en_US |
dc.type | Thesis | en_US |
dc.contributor.secondreader | Gondree, Mark | |
dc.contributor.department | Computer Science | |
dc.subject.author | High-Level Syntheis | en_US |
dc.subject.author | SystemC | en_US |
dc.subject.author | Trustworthy System Development | en_US |
dc.subject.author | Hardware-Oriented Security and Trust | en_US |
dc.subject.author | Ma-licious Hardware | en_US |
dc.subject.author | Electronic Design Automation | en_US |
dc.subject.author | Electronic System-Level Design | en_US |
dc.subject.author | Military Electronics | en_US |
dc.subject.author | Sup-ply Chain Security | en_US |
dc.description.service | Lieutenant, United States Navy | en_US |
etd.thesisdegree.name | Master of Science in Computer Science | en_US |
etd.thesisdegree.level | Masters | en_US |
etd.thesisdegree.discipline | Computer Science | en_US |
etd.thesisdegree.grantor | Naval Postgraduate School | en_US |
dc.description.distributionstatement | Approved for public release; distribution is unlimited. |
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