Fast Hardware Computation of x mod z
dc.contributor.author | Butler, J.T. | |
dc.contributor.author | Sasao, T. | |
dc.date.accessioned | 2015-06-30T17:41:31Z | |
dc.date.available | 2015-06-30T17:41:31Z | |
dc.date.issued | 2011-05 | |
dc.identifier.uri | http://hdl.handle.net/10945/45462 | |
dc.description.abstract | We show a high-speed hardware implementation of xmod z that can be pipelined in O(n ° m) stages, where x is represented in n bits and z is represented in m bits. It is suitable for large x. We offer two versions. In the first, the value of z is fixed by the hardware. For example, using this circuit, we show a random number generator that produces more than 11 million random numbers per second on the SRC-6 reconfigurable computer. In the second, z is an independent input. This is suitable for RNS number system applications, for example. The second version can be pipelined in O(n) stages. | en_US |
dc.publisher | Monterey, California: Naval Postgraduate School. | en_US |
dc.rights | This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States. | en_US |
dc.title | Fast Hardware Computation of x mod z | en_US |
dc.type | Article | en_US |
dc.contributor.department | Electrical and Computer Engineering | en_US |
dc.subject.author | x mod z computation | en_US |
dc.subject.author | high-speed modulo reduction | en_US |
dc.subject.author | mod z arithmetic | en_US |
dc.description.distributionstatement | Approved for public release; distribution is unlimited. |