Empirical Performance Comparison of Hardware and Software Task Context Switching
Schultz, Eric A.
Irvine, Cynthia E.
Shifflett, David J.
MetadataShow full item record
There are many divergent opinions regarding possible differences between the performance of hardware and software context switching implementations. However, there are no concrete empirical measures of their true differences. Using an empirical testing methodology, this research performed seven experiments, collecting quantitative performance results on hardware and software-based context switch implementations with two and four hardware privilege level support. The implementations measured are the hardware-based Intel IA-32 context switch, the software-based MINIX 3 context switch, a software-based simulation of a MINIX 3 context switch with four hardware privileged level support, and a software-based simulation of an Intel IA-32 hardware context switch. Experiments were executed using the Trusted Computing Exemplar Least Privilege Separation Kernel and the Linux 2.6 Kernel. The results include the number of cycles and time required to complete processing of each implementation. This study concludes that the hardware-based context switching mechanism is significantly slower than software implementation, even those that simulate the elaborate checks of the hardware implementation. A possible reason for this is posited.
Approved for public release; distribution unlimited.
Showing items related by title, author, creator and subject.
Greathouse, Carlus A. (Monterey, California. Naval Postgraduate School, 2008-03);This thesis describes a web-based continuous learning module (CLM) for use in introducing members of the Department of the Navy's acquisition community to software reuse in the context of Naval Open Architecture. The CLM ...
Levin, Timothy E.; Nguyen, Thuy D.; Benzel, Terry V.; Irvine, Cynthia E.; Clark, Paul C.; Bhaskara, Ganesha (Monterey, California. Naval Postgraduate School, 2006-07); NPS-CS-06-012The objective of this document is to begin to provide details and design issues that may arise while integrating Secret Protected (SP) with the SecureCore hardware and the SecureCore architecture. This document describes ...
Benzel, Terry V.; Irvine, Cynthia E.; Levin, Timothy E.; Nguyen, Thuy D.; Clark, Paul C.; Bhaskare, Ganesha (Monterey, California. Naval Postgraduate School, 2005-09); NPS-CS-05-010As a prelude to the clean-slate design for the SecureCore project, the fundamental security principles from more than four decades of research and development in information security technology were reviewed. As a result ...