A Programmable ASIC Design of a Low Sensitivity Sampled Data Filter
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In this paper, a CMOS custom Integrated Circuit featuring a multi-stage Universal Switched-Capacitor (SC) Filter is introduced. The network is based on the Generalized Immittance Converter (GIC) configuration, known for its excellent passive and active sensitivities. CMOS switches were used for elements relocation and are digitally controlled to select and realize different filter topologies. Switches were also used to control banks of binary-weighted capacitors that determine the filter center frequency, quality factor as well as its order. The bilinear transformation was utilized in the SC implementation of the filter resistive elements. Extra care was considered in the design procedure to minimize the effect of stray capacitors on the network transfer functions. The result was a general purpose digitally programmable multi-stage network that can equally compete with the best available stray insensitive filter. The design also inherits the low active and passive sensitivities the GIC enjoys.
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