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dc.contributor.advisorKragh, Frank
dc.contributor.advisorLoomis, Herschel
dc.contributor.authorWright, Durke A.
dc.date.accessioned2012-03-14T17:43:12Z
dc.date.available2012-03-14T17:43:12Z
dc.date.issued2009-03
dc.identifier.urihttp://hdl.handle.net/10945/4811
dc.descriptionApproved for public release, distribution unlimiteden_US
dc.description.abstractThere are existing wideband communications systems that were built using field programmable gate array (FPGA)-based software defined radio (SDR) designs. Despite the inherent advantages of these systems, some are functionally restricted by limited output bandwidth. This thesis was conceived in order to mitigate the restrictions imposed on such designs. This was accomplished by designing an FPGA-based SDR that can compress sampled intermediate frequency (IF) signals. The compression scheme used in the final design is based on flexible operator-defined time-frequency bins and independent energy thresholds for each bin. The thesis presents basic design concepts that influenced the development process, the final design implementation created using Xilinx's System Generator software, and the tests used to verify the final design's functional capabilities.en_US
dc.format.extentxviii, 107 p. : ill. (some col.) ;en_US
dc.publisherMonterey, California: Naval Postgraduate Schoolen_US
dc.subject.lcshSoftware radioen_US
dc.titleField programmable gate array (FPGA) based software defined radio (SDR) designen_US
dc.typeThesisen_US
dc.contributor.corporateNaval Postgraduate School (U.S.)
dc.description.serviceUS Navy (USN) author.en_US
dc.identifier.oclc319711886
etd.thesisdegree.nameM.S.en_US
etd.thesisdegree.levelMastersen_US
etd.thesisdegree.disciplineElectrical Engineeringen_US
etd.thesisdegree.grantorNaval Postgraduate Schoolen_US
etd.verifiednoen_US


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