SEU design considerations for MESFETs on LT GaAs

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Author
Weatherford, Todd R.
Radice, R.
Eskins, D.
Devers, J.
Fouts, D.J.
Marshall, P.W.
Marshall, C.J.
Dietrich, H.
Twigg, M.
Milano, R.
Date
1997-12
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Abstract
Computer simulation results are reported on transistor design and single-event charge collection modeling of metal­ semiconductor field effect transistors (MESFETs) fabricated in the Vitesse H-GaAsIII® process on Low Temperature grown (LT) GaAs epitaxial layers. Tradeoffs in Single Event Upset (SEU) immunity and transistor design are discussed. Effects due to active loads and diffusion barriers are examined.
Description
The article of record as published may be found at http://dx.doi.org/10.1109/23.659047
 
 
IEEE Transactions on Nuclear Science, V. 44, No. 6, pp. 2282-2289, December 1997
 
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.
URI
http://hdl.handle.net/10945/48746
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