Photonic analog-to-digital converters preprocessing using the robust symmetrical number system for direct digitization of antenna signals
Tong, Kee Leong
Pace, Phillip E.
Jenn, David C.
MetadataShow full item record
The need to realize pervasive battlespace awareness is placing an increasing demand on the bandwidth and resolution performance of modern sensors, communication receivers and electronic warfare. Fundamental to realizing this demand is the omnipresent highspeed analog-to-digital converters. The need constantly exists for converters with lower power consumption. To reduce the number of power-consuming components, high-performance ADCs employ parallel configuration of analog folding circuits to symmetrically fold the input signal prior to quantization by high-speed comparators. In this thesis, a prototype of an optical folding 6-bit ADC utilizing a 7-bit preprocessing architecture was implemented using the Robust Symmetrical Number System (RSNS). The RSNS preprocessing architecture is a modular scheme in which the integer values within each modulus (comparator states), when considered together, change one at a time at the next position i.e. Gray-code property. MATLAB simulations are used to help determine the properties of the RSNS. These properties include the dynamic range (largest number of distinct consecutive vectors) and the location of the dynamic range within the number system. Since the waveform repeats every fundamental period, a method that reduces all indexes to the 'lowest common denominator' is developed to find the symmetrical residues of each channel. Using the symmetrical residues determined, the corresponding DC shifts on each waveform can be calculated. The architecture employs a three-modulus (mod 7, 8, 9) scheme to preprocess the antenna signal. Electro-optic modulation of the input signal to generate the required number of folds within the dynamic range was successfully carried out in the three-modulus realization using modulators with a small half-wave voltage. The detection output are carefully aligned and postprocessed before amplitude analyzing with a high-speed comparator circuit responsible for the sampling and quantization of the signal (designed under a separate thesis). Low frequency analysis of the results using a 1 kHz input signal indicate a 5.42 effective number of bits (ENOB), a signal-to-noise ratio plus distortion (SINAD) of 34.42 dB, and a total harmonic distortion (THD) of -- 62.84 dB.
RightsThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.
Showing items related by title, author, creator and subject.
FPGA implementation of robust symmetrical number system in high-speed folding analog-to-digital converters Lim, Han Wei (Monterey, California. Naval Postgraduate School, 2010-12);Analog-To-Digital Converters (ADCs) are integral building blocks of most sensor and communication systems today. As the need for ADCs with faster conversion speeds and lower power dissipation increases, there is a growing ...
Tedesso, Thomas W. (Monterey California. Naval Postgraduate School, 2013-12);The use of symmetrical number systems and wideband technologies is investigated to develop novel concepts for use in electronic warfare (EW) receivers. A computationally efficient algorithm for determining the dynamic range ...
A Robust Symmetrical Number System with Gray code properties for applications in signal processing Akin, Ilker Aydin (Monterey, California. Naval Postgraduate School, 1996-09);A new symmetrical number system with applications in parallel signal processing is investigated. The Robust Symmetrical Number System (RSNS) is a modular system in which the integer values within each modulus, when considered ...