A fixed-point phase lock loop in a software defined radio
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Author
Johannes, Michael T.
Date
2002-09Advisor
Ha, Tri
Cristi, Roberto
Metadata
Show full item recordAbstract
A software defined radio is a much more flexible platform than traditional, hardware implemented radios. By implementing radio functions in software, and putting those functions on a Field Programmable Gate Array (FPGA) chip, users will have the ability to download mission specific radio capabilities. This thesis examines a fundamental piece of the receiver, the Phase-Lock Loop (PLL), simulates a software PLL, and investigates the effects of fixed- point versus floating point mathematics required for an FPGA based PLL. With a fixed-point PLL simulator, figures of merit such as lock-time, lock range, and pull-in range are determined for typical signal-to-noise ratio (SNR) levels.
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This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.Collections
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