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dc.contributor.advisorLoomis, Herschel H.
dc.contributor.advisorNewman, James H.
dc.contributor.authorWalker, Alan A. III
dc.date.accessioned2018-08-24T22:34:43Z
dc.date.available2018-08-24T22:34:43Z
dc.date.issued2018-06
dc.identifier.urihttp://hdl.handle.net/10945/59613
dc.description.abstractA satellite to be used as a testbed for experiments such as the Configurable Fault Tolerant Processor (CFTP) was designed at the Naval Postgraduate School. This processor consists of a Field Programmable Gate Array (FPGA), which may be reprogrammed by receiving a signal from a source external to the satellite. Experimentation of a high-speed pipelined and fault tolerant Fast Fourier Transform (FFT) was conducted for use within the CFTP. In this thesis, we detail the development and testing of a high-speed pipelined FFT in which fault tolerance can be applied at a later opportunity. Xilinx Vivado ISE® was utilized to synthesize behavioral Verilog to program an FPGA. Xilinx Vivado ISE’s® simulation suite produced waveforms to demonstrate functionality. Launch of CFTP is planned for FY18 aboard NPSat-1.en_US
dc.description.urihttp://archive.org/details/implementationof1094559613
dc.publisherMonterey, CA; Naval Postgraduate Schoolen_US
dc.rightsThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.en_US
dc.titleIMPLEMENTATION OF THE FAST FOURIER TRANSFORM ONBOARD CFTP-7 SPACE EXPERIMENTen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical and Computer Engineering (ECE)
dc.subject.authorFPGAen_US
dc.subject.authorNPSat-1en_US
dc.subject.authorsatelliteen_US
dc.subject.authorfault toleranceen_US
dc.subject.authorFFTen_US
dc.subject.authorDFTen_US
dc.subject.authorreprogrammable computersen_US
dc.subject.authorCFTPen_US
dc.subject.authorMidStar-1en_US
dc.subject.authorCFTP-1en_US
dc.subject.authorCFTP-7en_US
dc.subject.authorParseval’s theoremen_US
dc.description.serviceLieutenant, United States Navyen_US
etd.thesisdegree.nameMaster of Science in Electrical Engineeringen_US
etd.thesisdegree.levelMastersen_US
etd.thesisdegree.disciplineElectrical Engineeringen_US
etd.thesisdegree.grantorNaval Postgraduate Schoolen_US
dc.identifier.thesisid28475
dc.description.distributionstatementApproved for public release; distribution is unlimited.


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