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dc.contributor.advisorPace, Phillip E.
dc.contributor.advisorIatrou, Steven J.
dc.contributor.authorGrubbs, Hawken L.
dc.date.accessioned2018-08-24T22:35:27Z
dc.date.available2018-08-24T22:35:27Z
dc.date.issued2018-06
dc.identifier.urihttp://hdl.handle.net/10945/59670
dc.descriptionApproved for public release. distribution is unlimiteden_US
dc.description.abstractRadar systems often use low power, continuous waveform radio frequency (RF) modulations and require high-speed adaptive signal processors to provide the necessary processing gain to detect small radar cross-section targets in clutter on range-Doppler maps. Counter-radar technologies include digital RF memories (DRFMs) that attempt to provide multiple, structured false targets with clutter, for example, using a pipelined, finite impulse response arrangement of complex range bin processors. This thesis investigates high-capacity field-programmable gate array (FPGA) technology to enable on-the-fly flexibility and reconfigurability for both radar signal processing and DRFM electronic attack using a Xilinx Virtex Ultrascale+. A three-stage range, Doppler, post-detection integration radar modulation compression circuit is designed and quantified. A range compression circuit with a peak power consumption of 6.100W and a post-implementation utilization of 11% was designed. The Doppler filter bank was designed at 400 MHz with a peak power consumption of 2.688W and a post-implementation utilization of 9%. A coherent integration processor at 400 MHz had a peak power consumption of 2.517W and a post-implementation utilization of 9%. In addition, a DRFM complex range bin processor was designed and quantified at 500 MHz and had a peak power 2.543W with a post-implementation utilization of 11%.en_US
dc.description.sponsorshipCRUSERen_US
dc.description.urihttp://archive.org/details/fieldprogrammabl1094559670
dc.publisherMonterey, CA; Naval Postgraduate Schoolen_US
dc.rightsThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.en_US
dc.titleFIELD PROGRAMMABLE GATE ARRAY HIGH CAPACITY TECHNOLOGY FOR RADAR AND COUNTER-RADAR DRFM SIGNAL PROCESSINGen_US
dc.typeThesisen_US
dc.contributor.departmentInformation Sciences (IS)
dc.subject.authorLPI radaren_US
dc.subject.authorlow probability of intercept radaren_US
dc.subject.authorFPGAen_US
dc.subject.authorfield programmable gate arrayen_US
dc.subject.authorVirtex Ultrascale+en_US
dc.subject.authorVivadoen_US
dc.subject.authorSimulinken_US
dc.subject.authorDSPen_US
dc.subject.authordigital signal processingen_US
dc.subject.authorDRFMen_US
dc.subject.authorXilinxen_US
dc.description.recognitionOutstanding Thesisen_US
dc.description.serviceCaptain, United States Marine Corpsen_US
etd.thesisdegree.nameMaster of Science in Information Warfare Systems Engineeringen_US
etd.thesisdegree.levelMastersen_US
etd.thesisdegree.disciplineInformation Warfare Systems Engineeringen_US
etd.thesisdegree.grantorNaval Postgraduate Schoolen_US
dc.identifier.thesisid31650


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